--- /dev/null
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+ The Intercal Machine Machine Language Specification File\r
+ (c) 1990 Christian Brunschen,\r
+ a. k. a. d89cb@efd.lth.se\r
+\f\r
+This file contains the specifications for the Machine / Assembly Language\r
+used by the Intercal Machine Microprocesor, which closely follows the\r
+definition of the Intercal Compiler Language as defined by Woods/Lyon\r
+in 1972. It also contains ideas as to the actual implementation,\r
+hard- or softwarewise, of the Processor Instruction Set in an actual\r
+environment.\r
+\r
+It should be noted that the Intercal Machine Microprocessor is the first\r
+actual RISC processor (RISC being, of course, the acronym for\r
+Ridiculous Instruction Set Computer).\r
+\f\r
+Overview of processor capabilities / requirements\r
+\r
+Schematic overview of processor I/O busses:\r
+\r
+ +----------------\ /--------------+\r
+ _| \_/ |_\r
+ D +--- |_| D0 A04 |_| ---+\r
+ a | _| |_ |\r
+ t | |_| D1 A05 |_| |\r
+ a | _| |_ |\r
+ | |_| D2 A06 |_| |\r
+ b | _| |_ |\r
+ u | |_| D3 A07 |_| |\r
+ s ---+ _| |_ |\r
+ | |_| D4 A08 |_| |\r
+ 8 | _| |_ | A\r
+ | |_| D5 A09 |_| | d\r
+ b | _| |_ | d\r
+ i | |_| D6 A10 |_| | r\r
+ t | _| |_ | e\r
+ s +--- |_| D7 A11 |_| | s\r
+ _| |_ | s\r
+ |_| DACK A12 |_| |\r
+ _| |_ |\r
+ |_| GND A13 |_| |\r
+ _| _____ |_ | b\r
+ |_| RESET A14 |_| +--- u\r
+ _| ____ |_ | s\r
+ |_| MEM/WRLD A15 |_| |\r
+ _| _ |_ | 2\r
+ |_| R/W A16 |_| | 4\r
+ _| |_ |\r
+ |_| CLK A17 |_| | b\r
+ _| |_ | i\r
+ |_| VCC A18 |_| | t\r
+ _| |_ | s\r
+ |_| ERROR A19 |_| |\r
+ _| |_ |\r
+ +--- |_| A00 A20 |_| |\r
+ | _| |_ |\r
+ | |_| A01 A21 |_| |\r
+ | _| |_ |\r
+ | |_| A02 A22 |_| |\r
+ | _| |_ |\r
+ | |_| A03 A23 |_| |\r
+ | | | |\r
+ | +-----------------------------------+ |\r
+ | |\r
+ | |\r
+ +-------------------------------------------------+\r
+\r
+The only signals that might require some explanation are probably\r
+ _\r
+R/W : When this signal is low, The processor is reading data from the databus.\r
+ When it is high, the processor is driving the the databus.\r
+_____\r
+RESET : When this signal goes low, the processor is reset, and starts reading\r
+ incoming data from the databus, one byte each clock cycle, until the\r
+ line goes high again, at which time the processor will resume execution\r
+ of the program at memory location (Hex) 000000 (24 bits, remeber ?)\r
+ ____\r
+MEM/WRLD : _\r
+ Indicates the `target' or `source' (depending on the status of the R/W\r
+ line) of the data bus, sort of like an additional address bit. If this\r
+ line is low, the processor is communicating with the outside world. If\r
+ it is high, the processor is talking to its memory.\r
+\r
+DACK : Data ACKnowledge. Used when the processor communicates with the\r
+ outside world. Two cases:\r
+ a) Processor Talking\r
+ After the processor put the data on the databus, it will wait\r
+ until the DACK has been raised, and then dropped again. Then\r
+ it will put the next byte of data (if any) on the bus, or\r
+ proceed to the next instruction.\r
+ b) Processor listening\r
+ The same procedure as above, but in the other direction :\r
+ After the processor has read one byte of data, it quickly raises &\r
+ drops the line, and then expects the next data item to be present.\r
+\r
+ERROR : Indicates the fact that an error condition has occurred somewhere\r
+ in the program. The error number is present on the data bus.\r
+ After the error number has ben read, the address of the next statement\r
+ to be executed, had the eror not occurred, can be read in three\r
+ consecutive bytes from the databus.\r
+\f\r
+Processor Memory Management\r
+\r
+Since the Intercal Language provides quite a few interesting ways to manipulate\r
+arrays, stash and retrieve data, etc, all of which operations require\r
+manipulations of memory, and it was the intention of this implementation to\r
+provide an instruction set which immediately makes the average Intercal\r
+programmer feel right at home, quite a few very complex instructions have been\r
+provided.\r
+\f\r
+Intercal Machine Language Reference Part\r
+\r
+Summary of instructions:\r
+\r
+ABG ABstain from Gerund\r
+ABL ABstain from Label\r
+ALA ALlocate Aray\r
+BAA Begin Array Allocation\r
+BIA Begin Indexing Array\r
+BIN BINary operator\r
+CAL CALculate\r
+DLD Data LoaD\r
+EAA End Array Allocation\r
+FRG FoRGet\r
+IDA InDex Array\r
+IGN IGNore\r
+INS INitiate Statement\r
+NEX NEXt\r
+OST Open STorage\r
+PCT PerCenTage qualifier\r
+POP POP\r
+PPA PoP Array pointers\r
+PSA PuSh Array pointers\r
+PSH PuSH\r
+RDO ReaD Out\r
+REG Reinstate Gerund\r
+REL Reinstate Label\r
+RMB ReMemBer\r
+RSM ReSuMe\r
+RTV ReTrieVe\r
+STS STaSh\r
+UNO UNary Operator\r
+WRI WRite In\r
+\r
+General Format:\r
+\r
+ i i i i i p p s <optional arguments>\r
+\r
+where\r
+\r
+ i = instruction field\r
+ p = private field\r
+ s = size field\r
+\f\r
+ABstain from Label\r
+\r
+ABL Label\r
+\r
+ 0 1 1 1 1 0 0 0\r
+\r
+Sets the abstain bit of instruction at Label\r
+\f\r
+ABstain from Gerund\r
+\r
+ABG mnm\r
+\r
+ 0 1 1 1 1 1 0 0\r
+\r
+Sets the abstain bit of all statements whosde main instruction is mnm\r
+\f\r
+Allocate Array\r
+\r
+\r
+ALA #num\r
+ALA .var\r
+ALA :var\r
+ALA ,\r
+ALA ;\r
+ALA RES\r
+\r
+\r
+ 0 0 0 1 1 p p s\r
+\r
+where p p specifies the source,\r
+ 0 0 : immediate data <16 bits>\r
+ 0 1 : Variable <variable specifier, 16 bits>\r
+ 1 0 : Array, as pointed to by the Read Array Pointer\r
+ 1 1 : the contents of the RES register\r
+\r
+Takes the ALA argument, multiplies it with the current contents of the\r
+Temproary Register, and puts the result in the Temporary Register.\r
+\f\r
+Begin Allocating Array\r
+\r
+BAA ,var\r
+BAA ;var\r
+\r
+\r
+ 0 0 0 1 0 0 0 s\r
+ array specifier, 16 bits\r
+ jump offset, 16 bits\r
+\r
+Deallocates the memory block currently allocated to array `var', \r
+opens the Arrray Entry for array `var' for writing, and puts a pointer\r
+to the Array Entry in the Wite Array Data pointer register. If the array\r
+is being ignored, none of these things actually happen -- instead, the\r
+jump offset is added to the program counter.\r
+\f\r
+Begin Indexing Array\r
+\r
+BIA R ,var\r
+BIA W ,var\r
+BIA R ;var\r
+BIA W ;var\r
+\r
+\r
+ 0 0 1 0 1 0 t s\r
+ array specifier, 16 bits\r
+\r
+where t = type, 0 = Read or 1 = Write\r
+\r
+Sets the Read Array Data pointer to the address of the first array element,\r
+and the Read Array Dimension pointer to the first Dimension entry in the\r
+Array Table, thus preparing for further indexing.\r
+\f\r
+BINary operator\r
+\r
+BIN ~ Select\r
+BIN c\b/ Interleave,\r
+BIN $ aka Mingle\r
+\r
+ 0 1 1 0 0 t 0 0\r
+\r
+where t is the operation specifier:\r
+ 0 : Select\r
+ 1 : Interleave / Mingle\r
+\r
+The operation is performed on the OP1 and OP2 registers, and the result is\r
+placed in the RES register.\r
+\f\r
+CALculate\r
+\r
+CAL .\r
+CAL :\r
+CAL ,\r
+CAL ;\r
+\r
+\r
+ 0 1 0 1 0 0 0 s\r
+\r
+Puts the contents of the RES register in the memory location pointed to by\r
+the Write Array Data pointer\r
+\f\r
+Data LoaD\r
+\r
+DLD t #num\r
+DLD t .var\r
+DLD t :var\r
+DLD t ,\r
+DLD t ;\r
+DLD t RES\r
+\r
+\r
+ 0 1 0 0 t p p s\r
+\r
+where t = target register, 0 = OP1 or 1 = OP2\r
+ p p = source :\r
+ 0 0 : Immediate data <16 bits>\r
+ 0 1 : Variable <specifier, 16 bits>\r
+ 1 0 : Array item (as indexed by the Read Array Data pointer)\r
+ 1 1 : RES register\r
+\r
+Loads the target register with the contents of the source\r
+\f\r
+End Allocating Array\r
+\r
+EAA\r
+\r
+\r
+ 0 0 1 0 0 0 0 0\r
+\r
+Allocates a chunk of memory to the size of\r
+\f\r
+FoRGet\r
+\r
+FRG #num\r
+FRG .var\r
+FRG :var\r
+FRG ,\r
+FRG ;\r
+FRG RES\r
+\r
+\r
+ 1 0 0 0 0 p p s\r
+\r
+where p p = source :\r
+ 0 0 : Immediate <16 bits>\r
+ 0 1 : variable <specifier, 16 bits>\r
+ 1 0 : array (as indexed by the Read Array Data pointer)\r
+ 1 1 : RES register\r
+\r
+Pops source number of addresses from the stack, discarding them.\r
+\f\r
+InDex Array\r
+IDA R #num\r
+IDA W #num\r
+IDA R .var\r
+IDA W .var\r
+IDA R :var\r
+IDA W :var\r
+IDA R RES\r
+IDA W RES\r
+\r
+\r
+ 0 0 1 1 t p p s\r
+\r
+where t = type, 0 = Read or 1 = Write\r
+ p p = source :\r
+ 0 0 : Immediate Data <16 bits>\r
+ 0 1 : variable <specifier, 16 bits>\r
+ 1 0 : ILLEGAL\r
+ 1 1 : RES register\r
+\r
+Takes the Array Dimension (i.e, what the Array Dimension Pointer points to),\r
+adds (#num or RES) instances of it to the Array Data Pointer, and adds 2 to the\r
+Array Dimension Pointer.\r
+\f\r
+IGNore\r
+\r
+IGN .var\r
+IGN :var\r
+IGN ,var\r
+IGN ;var\r
+\r
+ 1 0 1 0 1 0 0 s\r
+ variable specifier, 16 bits\r
+\r
+Sets the ignore flag of the variable specified\r
+\f\r
+INitiate Statement\r
+\r
+INS mnm Label\r
+\r
+where `mnm' is one of the following 3-character mnemonics:\r
+\r
+ABS ABStain\r
+REI REInstate\r
+CAL CALculate\r
+NEX NEXt\r
+FRG FoRGet\r
+RES RESume\r
+STS STaSh\r
+RTV ReTrieVe\r
+IGN IGNore\r
+RMB ReMemBer\r
+WRI WRite In\r
+RDO ReaD Out\r
+\r
+\r
+ 1 1 1 p p p p p\r
+ 2 bytes :\r
+ a o o o o o o o o o o o o o o o\r
+\r
+where p p p p p = major instruction opcode\r
+\r
+where a is the abstain bit of the instruction : set if this instruction\r
+is to be abstained from. The remaining 15 bits are the jump offset, which will\r
+be added to the program counter should the instruction be abstained from.\r
+It is presumed that no statement will result in code exceeding 32.767 bytes.\r
+\f\r
+NEXt\r
+\r
+NEX Label\r
+\r
+ 0 1 1 0 1 0 0 0\r
+ Target Address, 24 bits\r
+\r
+Pushes the address of the next instruction on the return stack and puts the\r
+Target addres in the Program counter\r
+\f\r
+Open STorage\r
+\r
+OST .var Label\r
+OST :var Label\r
+OST ,var Label\r
+OST ;var Label\r
+\r
+\r
+ 0 0 0 0 1 0 0 s\r
+ variable/array specifier, 16 bits\r
+ jump offset, 8 bits\r
+\r
+\r
+Trys to open the specified variable for writing.\r
+If it being ignored (i.e, its ignore flag is set) the jump offset is\r
+added to the program counter.\r
+If it is an array, the Write Array Data pointer is set to the address\r
+of the first element of the array, and the Write Array Dimension pointer\r
+to the first dimension entry in the Array Table.\r
+If it is a Variable, the Write Array Data pointer is set to the address\r
+of the Variable.\r
+\f\r
+PerCenTage qualifier\r
+\r
+PCT #num Label\r
+\r
+\r
+ 0 0 0 0 0 0 0 0\r
+ 0 c c c c c c c\r
+ Jump offset, 16 bits\r
+\r
+where c c c c c c c is a 7 bit binary number between 0 and 100\r
+\r
+Gets a random number in the range 0 .. 99, compares it to the percent chance\r
+and acts on the result:\r
+- if the random number is less than the percent chance, nothing is done\r
+- if it is equal or greater, the jump offset is added to the program counter\r
+\f\r
+POP\r
+\r
+POP\r
+\r
+\r
+ 1 1 0 0 0 0 1 0\r
+\r
+Gets the top item on the stack and puts it in the RES register -- 32 bits\r
+\f\r
+PoP Array pointers\r
+\r
+PPA\r
+\r
+ 1 1 0 0 1 0 1 0\r
+\r
+Retrieves the contents of the Read Array Data pointer from the stack\r
+\f\r
+PuSh Array pointers\r
+\r
+PSA\r
+\r
+\r
+ 1 1 0 0 1 0 0 0\r
+\r
+Pushes the contents of the Read Array Data pointer to an internal stack\r
+\f\r
+PuSH\r
+\r
+PSH\r
+\r
+\r
+ 1 1 0 0 0 0 0 0\r
+\r
+Pushes the RES register to the stack -- 32 bits\r
+\f\r
+ReaD Out\r
+\r
+RDO #num\r
+RDO .var\r
+RDO :var\r
+RDO ,\r
+RDO ;\r
+RDO RES\r
+\r
+\r
+ 1 0 1 1 1 p p s\r
+\r
+where p p = source:\r
+ 0 0 : Immediate <16 bits>\r
+ 0 1 : Variable <specifier, 16 bits>\r
+ 1 0 : Array (as pointed to by the Read Array Data pointer)\r
+ 1 1 : RES register\r
+\r
+Writes 2 or 4 bytes (16 or 32 bits) on the data bus\r
+\f\r
+REinstate Gerund\r
+\r
+REG mnm\r
+\r
+ 0 1 1 1 0 1 0 0\r
+ operation specifier, 8 bits\r
+\r
+In this form, the hole program will be searched to find instructions of the\r
+specified type, and their abstain bits will be reset.\r
+\f\r
+REinstate Label\r
+\r
+REL Label\r
+\r
+ 0 1 1 1 0 0 0 0\r
+ Label, 24 bits\r
+\r
+In this form, the instruction at the address of Label will have its abstain\r
+bit set/reset.\r
+\f\r
+ReMemBer\r
+\r
+RMB .var\r
+RMB :var\r
+RMB ,var\r
+RMB ;var\r
+\r
+ 1 0 1 0 0 0 0 s\r
+ variable specifier, 16 bits\r
+\r
+Clears the specified variable's ignore flag\r
+\f\r
+ReSuMe\r
+\r
+RSM #num\r
+RSM .var\r
+RSM :var\r
+RSM ,\r
+RSM ;\r
+RSM RES\r
+\r
+ 1 0 0 0 1 p p s\r
+\r
+where p p = source :\r
+ 0 0 : Immediate <16 bits>\r
+ 0 1 : variable <specifier, 16 bits>\r
+ 1 0 : array (as indexed by the Read Array Data pointer)\r
+ 1 1 : RES register\r
+\r
+Pops source number of addresses from the stack.\r
+If there are less than `source' items on the stack, the procesor is halted\r
+and an error signaled\r
+If no error occurs, the last popped address is NOT discarded, but instead\r
+placed in the Program counter.\r
+\f\r
+ReTrieVe\r
+\r
+RTV .var\r
+RTV :var\r
+RTV ,var\r
+RTV ;var\r
+\r
+ 1 0 0 1 1 0 0 s\r
+ Variable/Array Specifier, 16 bits\r
+\r
+Retrieves the latest stashed instance of the variable or array specified\r
+\f\r
+STaSh\r
+\r
+STS .var\r
+STS :var\r
+STS ,var\r
+STS ;var\r
+\r
+ 1 0 0 1 0 0 0 s\r
+ Variable/Array specifier, 16 bits\r
+\r
+Stashes the variable or array specified\r
+\f\r
+UNary Operator\r
+\r
+UNO & AND\r
+UNO V OR\r
+UNO V\b- XOR\r
+UNO ? XOR\r
+\r
+ 0 1 0 1 1 t t s\r
+\r
+where t is the operation specifier:\r
+ 00 : AND\r
+ 01 : OR\r
+ 10 : XOR\r
+ 11 : Illegal\r
+\r
+The specified operation is performed on the RESult register, leaving it there.\r
+\f\r
+WRite In\r
+\r
+WRI .\r
+WRI :\r
+WRI ,\r
+WRI ;\r
+\r
+\r
+ 1 0 1 1 0 0 0 s\r
+\r
+Reads 2 or 4 bytes (16 or 32 bits) from the data bus and puts them in\r
+the variable pointed to by the Write Array Data pointer\r
+\f\r
projects / intercal.git / commitdiff